2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator
نویسندگان
چکیده
منابع مشابه
A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector
A clock and data recovery (CDR) circuit using a new halfrate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-μm N-well CMOS technique. Experimental r...
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We have previously described a design for a 4Gb/s signaling system that uses transmitter equalization to overcome the frequency-dependent attenuation due to skin effect in transmission lines. We present here experimental results from an implementation of this idea in 0.5μ CMOS, showing the effectiveness of a simple transition-filter equalization technique. Our experimental chips use a tracking ...
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ژورنال
عنوان ژورنال: Advances in Radio Science
سال: 2006
ISSN: 1684-9973
DOI: 10.5194/ars-4-287-2006